The present invention relates to a method of fabricating a semiconductor memory device, and more particularly to a method of eliminating weakness caused by high-density plasma (HDP) dielectric layer.
Memory technology has progressed considerably in recent years. Since the operational speed and the manipulation data amount of a central processing unit (CPU) is increasing, the performance of a memory cell is increasing at the same time. For example, high speed erasing is a popular method for improving the performance of a memory. Volatile storage memories, such as random access memories (RAM), are widely used in computer nowadays. However, the stored data in RAM vanishes while the power is broke off. Another nonvolatile storage memories, such as mask read only memory (Mask ROM), erasable programmable ROM (EPROM), or electrically erasable programmable ROM (EEPROM) will not lost the stored messages when power dismissed and will be better for some specific usage.
Flash memories are also a nonvolatile storage memory, which has similar structure than conventional EEPROMs. They have a very high erasing speed feature in either an overall region or a local region thereof, and therefore they are very popularly applied in the computer field. For example, they are used to replace the read-only memories to store the firmware such as BIOS (basic input/output system). The users can easily update their BIOS by rewriting the flash memory.
Conventional flash memory cells have a double or triple layer of polysilicon structure. The lower most polysilicon layer is patterned to form the floating gates, and the second polysilicon layer is patterned to form the control gates and the word lines structure. A third polysilicon layer is patterned as select gates to form the triple layer polysilicon structure.
Typically, in procedure of fabricating the flash memory cells, a silicon oxide layer, a polysilicon layer and a nitride layer are formed in sequence on a semiconductor substrate. These layers are then defined and patterned by conventional photolithography and etching technology to form a plurality of parallel stacked gate layers. A high-density plasma (HDP) oxide layer is subsequently formed to cover the stacked gate layers and fill the trenches between the stacked gate layers to server as an insulating layer. A portion of the HDP oxide layer is removed by wet etching back process until exposing the nitride layer. The exposed nitride layer is then removed by wet etching process. The word line control gates are subsequently formed in the following processes.
During producing the HDP oxide layer, since the high stress characteristic from the inherent property of the nitride layer, weakness and dislocation defect is easily formed to the HDP oxide layer, and a crack issue is readily generated between the HDP oxide layer and the nitride layer. Moreover, during the wet etching process of removing the HDP oxide layer and the nitride layer, the etchant easily encroaches the underlying polysilicon layer along the interface between the HDP oxide layer and the nitride layer, and unfortunately further encroaches the bit line region surface besides the stacked gate layer. A gap is therefore formed between the HDP oxide layer and the nitride layer. During fabricating the word line control gate in following processes, a portion of polysilicon for forming control gate is deposited into the gap, which causes a short between the floating gate and bit lines. Therefore, some coupling charges in the floating are lost form the bit lines during memory operating, so that bit line leakage issue is occurred and results in data storage failure of the memory.
The present invention provides a method of eliminating weakness caused by high-density plasma (HDP) dielectric layer. A thin hot thermal oxide (HTO) layer is formed on a semiconductor substrate before forming the HDP dielectric layer. The HTO layer can release the stress between the HDP dielectric layer and a nitride layer, and protect the sidewall of a stacked gate layer formed on the semiconductor substrate to prevent defects and gaps thereon in the subsequent etching process.
In one aspect, the present invention provides a method of eliminating weakness caused by high density plasma (HDP) dielectric layer adapted for a semiconductor substrate including a stacked gate layer of which having a silicon nitride cap layer on the top. The method comprises the following steps. A hot thermal oxide (HTO) layer covering the stacked gate layer is conformally formed over the semiconductor substrate. The HDP dielectric layer is subsequently formed on the HTO layer.
In another aspect, the present invention provides a method of fabricating a semiconductor memory device. The method at least comprises the following steps. At least one stacked gate layer is formed on a semiconductor substrate, and each stacked gate layer has a cap nitride layer on the top. Bit lines are formed in the semiconductor substrate on both sides of the stacked gate layer. A hot thermal oxide (HTO) layer covering the stacked gate layer and the bit lines is conformally formed over the semiconductor substrate. A high density plasma (HDP) dielectric layer is formed on the HTO layer.
In another aspect, the present invention also provides a method of fabricating a semiconductor memory device. The method at least comprises the following steps. A gate oxide layer, a polysilicon layer and a nitride layer are formed on a semiconductor substrate, and then patterned to form a plurality of stacked gate layers. A plurality of bit lines is formed in the semiconductor substrate on both sides of the stacked gate layers. A hot thermal oxide (HTO) layer covering the stacked gate layer and the bit lines are conformally formed over the semiconductor substrate. A high density plasma (HDP) dielectric layer is formed on the HTO layer. A portion of the HDP dielectric layer is removed until exposing the nitride layer, and then the nitride layer is removed.
The HTO layer of the present invention is formed by low pressure chemical vapor deposition (LPCVD) at a high temperature of about 600-1000 degrees, and does not consume the surface silicon layer on the semiconductor substrate.